The present disclosure relates generally to semiconductor technology, and more particularly, to low and high voltage devices and method of making the same.
The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
As semiconductor circuits such as complementary metal-oxide-semiconductor field effect transistors (CMOSFETs) are adapted for high voltage applications, several approaches have been utilized for incorporating a high voltage device with a low voltage device (e.g., logic device or memory device) for system-on-chip (SoC) technology. One approach cascodes two or more transistors to achieve the required high voltage capability. Another approach utilizes additional process steps/masks to fabricate high voltage transistors (e.g., laterally diffused MOS transistor) that are integrated in current CMOS process technology. Although these approaches have been satisfactory for their intended purposes, they have not been satisfactory in all respects. For example, cascoding two or more transistor requires a larger footprint (chip area) and complex circuitry to generate multiple bias voltages to support nodes between the cascoded transistors, consumes higher power, and exhibits poor high frequency behavior.